Today on The Bandwidth-Bound, following the hybrid cache bookkeeping bugs we tracked over the weekend, the local inference ecosystem is taking a sharp mathematical turn toward state-space memory hacks. Systems engineers are proving that stochastic rounding and closed-form linear cache translations can effectively eliminate redundant long-context prefilling across hybrid architectures.
A study published on Monday, November 9, 2026 (arXiv:2611.05432) details mechanisms for translating key-value caches and recurrent states directly between heterogeneous hybrid-attention language models at the 16B–48B scale. The research evaluates model pairs including Kimi-VL-A3B and Kimi-Linear-48B (utilizing Multi-Head Latent Attention and Kimi Delta Attention) alongside Qwen3.5-27B and Qwen3.8-27B (using Gated DeltaNet). By mapping MLA latents via token-wise linear projections and copying recurrent states with closed-form corrections, target models take over multi-turn sessions without re-reading history, reducing time-to-first-token by 18.7x to 46.8x at 64K tokens.
Why it matters
For practitioners serving local agents or orchestrating multi-model pipelines, transferring conversational context across model boundaries has historically required complete prefill passes. Demonstrating that compressed latents and linear-attention states can be mathematically mapped rather than computed from raw prompt text offers a clear mechanism for zero-prefill model handoffs. This approach significantly reduces initial token latency and memory bandwidth consumption during mid-session context transfers.
The authors frame the closed-form translation matrix as a mathematically robust bridge that preserves output distribution fidelity across model generations. However, independent systems engineers note that cross-model state mapping depends on strictly aligned layer topologies, leaving open questions about how robustly linear conversions hold up under fine-tuned or pruned weight variations.
Research published on Monday, November 9, 2026, analyzed the impact of bf16 recurrent state precision across six open hybrid reasoning models evaluated on 590 math problems. The findings show that standard round-to-nearest (RTN) in bf16 state formatting causes five out of six models to enter verbose generation loops and hit 32K token caps, dropping Qwen3.5-9B accuracy from 85.6% to 70.8%. Replacing RTN with stochastic rounding (SR)—implemented using a low-overhead integer-hash random generator—completely removes the length expansion and restores performance to FP32 baselines without increasing state memory requirements.
Why it matters
As open-weight hybrid models interleave standard attention with recurrent linear mixers like Mamba-2 and Gated DeltaNet, small numerical errors in cached recurrent states accumulate across long sequence steps. The discovery that bf16 rounding bias triggers infinite generation loops provides an immediate fix for serving engine maintainers. Implementing stochastic rounding in state update kernels recovers full baseline accuracy while keeping memory bandwidth demands strictly at 16 bits per element.
The paper's authors argue that benchmark evaluations for hybrid sequence architectures must mandate reporting state dtypes and cap rates due to hidden precision degradation. Conversely, runtime developers express caution regarding the compute overhead of pseudo-random hash generation inside fused Triton and CUDA scan kernels on consumer hardware.
Details presented on Monday, November 9, 2026, introduce FlashState, an inference serving system that uses Arbitrary State Checkpointing (ASC) to disconnect recurrent state snapshot positions from fixed KV-cache block boundaries in hybrid LLMs. By framing state management as a memory-constrained optimization problem paired with a cost-aware online eviction policy, FlashState achieved 3.14x, 2.27x, and 1.54x prefill throughput increases over vLLM when serving GLM-5.3-Flash, Nemotron 3 Super, and Qwen3.8-Flash-Next on NVIDIA B200 GPUs.
Why it matters
Hybrid models combining transformer attention with linear recurrent layers suffer from severe prefill redundant compute during multi-turn agent sessions because standard prefix caching requires aligned block boundaries. Decoupling recurrent checkpoint placement from KV cache page sizes resolves time-to-first-token spikes in multi-turn coding agent loops. This provides a clear architectural path for scaling concurrent agent workloads on high-density GPUs.
The FlashState authors demonstrate that fine-grained state capture yields massive throughput gains by eliminating repeated prefills on partial prompt overlaps. In contrast, serving engine maintainers highlight the increased complexity of managing dynamic, unaligned state pointers alongside standard paged memory allocators.
Verified across 2 sources:
X(Nov 9) · arXiv(Nov 9)
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Perplexity all work well.
A profiling report posted to the `vllm-ascend` repository on Monday, November 9, 2026, analyzed performance bottlenecks when running Qwen3.8-27B (configured with 48 linear-attention layers and 16 full-attention layers) on Ascend 950DT hardware. The profiling revealed that the `RecurrentGatedDeltaRule` execution kernel consumes ~8.7 ms per decode step, accounting for 12–15% of total decode latency and exceeding the memory-bandwidth weight streaming floor. The author confirmed that intermediate state writes cannot be skipped because speculative decoding frameworks (MTP/EAGLE) require draft models to read state slots across all proposed draft positions.
Why it matters
While linear-attention hybrid architectures reduce memory footprints by bounding KV cache growth, their actual decode throughput is heavily governed by the execution efficiency of recurrent state update kernels. Identifying that state writes dominate the critical path due to speculative decoding dependencies informs hardware-specific fused kernel development. It demonstrates that theoretical linear-attention speedups depend strictly on fused compute execution.
The profiling engineer notes that optimizing the recurrent delta rule kernel offers immediate throughput headroom since its execution currently exceeds memory streaming bounds. Systems maintainers argue that supporting multi-token speculative decoding forces unavoidable state writebacks, limiting how aggressively recurrent state updates can be fused.
Researchers released details on Monday, November 9, 2026, for Cross-Layer TopK (CLT), a methodology that replaces uniform per-layer L0 budgets with a global per-token sparsity allocation during transcoder training. Evaluated on Qwen3-8B-Base, CLT achieved a lower Fraction of Variance Unexplained (FVU) while using 20% fewer active latents than JumpReLU transcoders. The fixed total L0 budget matches sparse decoding pipelines, yielding a 2.9x training speedup per step while generating complete computational circuits with higher replacement scores. The model weights have been published open-source.
Why it matters
Mechanistic interpretability pipelines using transcoders have been constrained by uniform layer sparsity assumptions, even though middle transformer layers exhibit higher reconstruction complexity. Dynamic global L0 allocation makes circuit-tracing over open models significantly more computationally viable. The accompanying 2.9x training speedup and released Qwen3-8B weights give interpretability researchers a reproducible foundation for mapping feature propagation across layers.
The authors emphasize that global L0 budgeting reflects the natural variability of layer-wise feature density, producing higher circuit completeness. Interpretability practitioners note, however, that dynamic cross-layer allocation complicates comparative layer-by-layer feature tracking since latent counts shift dynamically depending on input token context.
An updated preprint published on Friday, November 6, 2026, introduced Subspace-Aware Sparse Autoencoders (SASA). The authors address a structural flaw in standard SAEs, which assign each latent feature a single decoder direction under the assumption that features are one-dimensional—a cause of severe feature splitting when internal representations span multi-dimensional subspaces. SASA replaces single-vector decoders with learned sub-spaces, enforcing sparsity via Top-s group gating and group-rank nuclear-norm regularization. Evaluations on GPT-2 and Mistral-7B confirmed reduced feature absorption over standard SAE baselines.
Why it matters
Standard sparse autoencoders frequently fragment complex multi-dimensional concepts into multiple redundant 1D latent vectors, distorting circuit analysis. Moving to subspace-aware decoders provides a geometrically faithful mapping of internal feature spaces in models like Mistral-7B. This gives interpretability researchers clean feature representations for probe design and model editing.
The authors demonstrate that subspace decoders prevent feature splitting and absorb less variance than standard 1D dictionary learning. Interpretability tool builders note that tracking multi-dimensional feature subspaces increases dictionary parameter counts and complicates automated auto-interpretation labeling scripts.
Research published on Monday, November 9, 2026, presented a calibrated concept profiling framework designed to evaluate direct neuron activations in open language models without intermediate sparse autoencoders. By generating stimulus prompt batteries from a declared reference corpus distribution and evaluating activations across dual passes, the method computes a single noise-bounded activation score per neuron in units of standard deviation. Evaluated on OpenCoder-1.5B across training checkpoints spanning 2 trillion tokens, the released codebase provides statistical baselines and chance-level thresholds for direct neuron interpretation.
Why it matters
Given recent critiques regarding feature absorption and reconstruction artifacts in secondary probes and SAEs, direct neuron measurement offers a more grounded baseline for interpretability workflows. Providing reproducible prompt batteries and released analysis code enables researchers to track concept representations across training checkpoints. This strengthens the open-source toolkit for inspecting raw model weights.
Wilam demonstrates that calibrated stimulus batteries yield statistical confidence bounds for individual neuron firings without dictionary training. Interpretability researchers note, however, that direct neuron profiling remains subject to polysemanticity, where individual neurons activate across multiple unrelated concept domains.
Comparative evaluation reports published on Sunday, November 8, 2026, across the Harness Leaderboard (28,849 trials) and Garry Tan's coding harness benchmark demonstrate that agent scaffolding exerts a dominant effect on task success and token costs. While seven distinct coding harness configurations evaluating Claude Opus on 20 tasks yielded similar completion rates (71% to 79%), execution costs varied widely from $0.19 to $0.44 per solved task. On the Harness Leaderboard, swapping the surrounding software harness while holding open-weight base models fixed caused average task pass rates to swing from 27.3% to 51.4%.
Why it matters
This data indicates that agent capability is frequently bounded by harness infrastructure—including context retrieval, tool routing, and verification loops—rather than raw foundation model intelligence alone. For developers building agent tooling, focusing on harness optimization and minimal execution loops delivers larger cost and accuracy gains than continually upgrading API model tiers. It also highlights that comparative agent benchmarks are invalid unless harness parameters are strictly controlled.
Benchmarking researchers emphasize that harness design is the primary leverage point for agent performance, showing that lightweight scaffolding can make smaller models outperform un-harnessed frontier models. Conversely, framework developers point out that complex, multi-agent harnesses often introduce significant token bloat and log flooding, inflating execution costs without providing proportional accuracy gains.
Verified across 2 sources:
i10x(Nov 9) · GitHub(Nov 8)
Click Copy for AI above, then paste the prompt
into your favorite AI chatbot — ChatGPT, Claude, Gemini, or
Perplexity all work well.
A paper from UC Berkeley's Sky Computing Lab published on Tuesday, October 27, 2026 (analyzed November 9) introduced 'Evolving Agent Teams'. The system uses a supervisor agent that dynamically restructures multi-agent task graphs and worker assignments mid-execution rather than relying on fixed agent roles. Applied to GPU kernel optimization across NVIDIA, AMD, and Apple hardware, the dynamic teams achieved a 1.21x geometric mean speedup over production FlashInfer kernels across 36 of 47 workloads and outperformed vLLM by 3.01x on AMD MI350X accelerators, utilizing a persistent filesystem for cross-run optimization memory.
Why it matters
The study demonstrates that static multi-agent topologies underperform single-agent baselines under matched token budgets due to rigid communication overhead. Allowing a supervisor agent to dynamically spawn, merge, or terminate worker roles based on intermediate execution feedback unlocks superior performance on low-level coding tasks. This provides an architectural model for building dynamic agent orchestration harnesses.
The Sky Computing Lab researchers argue that dynamic structural adaptation paired with persistent filesystem memory is essential for long-horizon engineering tasks. In contrast, agent framework developers warn that unconstrained dynamic agent spawning increases API token consumption and risks infinite execution loops if supervisor termination conditions fail.
The release of `llama-modchip` v2.4.0 on Sunday, November 8, 2026, introduced a set of `ggml` kernel patches and custom quantization tools enabling the 284.33B parameter DeepSeek-V4-Flash model (13.17B active parameters) to execute on a 64GB CPU system without a GPU. The engine compresses the checkpoint to 56.56 GiB using an aggressive 1.71 bits-per-weight format (SwiGLU-H2 + Fractal-64), maintaining peak VmRSS under 59 GiB across a 256K context. Benchmarks on a Zen 5 16-core CPU show prefill processing at 44.4 tok/s and generation at 9.1–14.7 tok/s using AVX-512BW kernels, though custom tensor type 40 renders the files incompatible with stock GGUF loaders.
Why it matters
This release demonstrates that multi-hundred-billion parameter Mixture-of-Experts architectures can be compressed to run entirely within standard desktop DDR5 RAM budgets. For local practitioners, it proves the feasibility of hosting frontier-scale reasoning models for offline code analysis without expensive GPU clusters. However, non-standard quantization formats complicate integration with standard tools like Ollama or LM Studio.
The project developer highlights that extreme low-bit quantization combined with AVX-512 vectorization unlocks CPU hosting for massive MoEs previously restricted to enterprise clusters. Independent technical reviews point out, however, that redefining GGUF tensor structures breaks upstream ecosystem compatibility and relies on aggressive IQ1_S expert truncation that requires thorough accuracy auditing.
Developer release notes published on Tuesday, November 10, 2026, introduced TokenRace (`uvx tokenrace`), an open-source benchmarking tool designed to resolve discrepancies in local LLM performance reporting. By moving stopwatch timing to the client side via Python's `time.perf_counter()`, the tool standardizes throughput measurements across 15 inference runtimes (including Ollama, LM Studio, llama.cpp, and oMLX). Initial testing on an Apple M5 Pro Mac (24 GB RAM) running LFM3 1.7B at 8-bit precision showed tight performance clustering (oMLX at 129.1 tok/s vs. Ollama at 113.9 tok/s), proving that internal server metrics often misreport performance by inconsistently measuring prompt processing and first-token latency.
Why it matters
Local LLM practitioners frequently encounter non-reproducible performance numbers because serving engines exclude prefill passes or first-token generation delays from internal logging. Client-side timing controls for prompt caching, warm versus cold starts, and reasoning outputs, providing reliable real-world latency data. This allows developers to select inference runtimes based on actual application performance rather than synthetic server logs.
The tool's creator highlights that uniform client-side timing reveals that major inference engines perform much closer to parity than isolated server benchmarks suggest. Conversely, engine maintainers point out that client-side network sockets introduce minor IPC latency overheads that do not reflect raw execution kernel speed.
Issue reports submitted to NVIDIA's `TensorRT-Model-Connect` repository on Monday, November 9, 2026, documented severe latency regressions in model implementations including LFM2 and Llama-3.1-Minitron-4B. Profiling on NVIDIA GB10 hardware showed that decode step latency scales linearly with total pre-allocated KV cache capacity rather than active sequence length. For short prompts executed within a 32,768-row allocated cache, per-request times rose from 0.40s to 18.6s due to attention routines executing score matrix multiplications and mask selections across unallocated cache slots.
Why it matters
This bug highlights an operational pitfall in inference runtime design where static memory pre-allocation unintentionally forces dense attention operations over unpopulated KV cache blocks. For systems engineers deploying local models, unmasking unallocated cache capacity negates the speed advantages of small base architectures. Fixing bound allocations restores expected decode performance during short-turn agent interactions.
The bug reporter showed that runtime binding logic in `kv_cache.cpp` failed to truncate sequence loops to active token counts, forcing full-capacity matrix sweeps. NVIDIA maintainers confirmed the behavior and noted that prefix-bucketing fixes are being ported from other model families to resolve the dynamic allocation bounds.
Verified across 2 sources:
GitHub(Nov 9) · GitHub(Nov 9)
Click Copy for AI above, then paste the prompt
into your favorite AI chatbot — ChatGPT, Claude, Gemini, or
Perplexity all work well.
Researchers published 'Transformer-FSQ' on Monday, November 9, 2026, introducing finite scalar quantization to compress key-value caches in transformer architectures. By replacing traditional continuous projection heads with a scalar quantization bottleneck that stores discrete integer codes per token without per-token scaling metadata, the method achieves 12x to 97.5x memory compression on long-context retrieval workloads. A custom fused Triton kernel decodes attention scores directly from the discrete integer representations during inference.
Why it matters
Key-value cache growth represents the primary VRAM bottleneck during long-context local generation, frequently surpassing model weight footprints. By eliminating per-token metadata overhead and deploying direct Triton decoding kernels, Transformer-FSQ enables consumer GPUs to hold massive context windows without requiring severe sequence truncation or offloading to host RAM.
The authors argue that replacing continuous projections with discrete scalar codebooks eliminates metadata scaling overhead while retaining long-context retrieval accuracy. Systems researchers note, however, that non-standard vector quantizations require custom attention kernels, limiting immediate drop-in adoption across mainstream runtimes like vLLM or llama.cpp.
A study published on Monday, November 9, 2026, by MIT CSAIL researchers demonstrated Weight-Space Programming (WSP), where frontier language models analyze and modify raw neural network weight matrices without backpropagation or training loops. Using static tensor analysis, SVD, and activation patching to locate fault directions, the system surgically edits weight parameters. In one trial, modifying 0.016% (1,023 parameters) of Qwen3.5-0.8B's weights increased its MATH-500 score from 7.9% to 48.1%, though 6 out of 16 experimental trajectories failed to yield overall improvements.
Why it matters
This work bypasses traditional gradient-based fine-tuning by treating model weight matrices as readable and editable code targets for automated agents. For interpretability researchers, it offers a concrete demonstration of using internal activation geometries to execute non-gradient model repairs. However, the high trajectory failure rate highlights that direct tensor manipulation remains brittle across varied prompt distributions.
The MIT CSAIL research team views direct weight manipulation as a new paradigm for automated self-editing and mechanistic alignment without dataset curation. Conversely, critical technical reviews point out that localized parameter edits frequently cause unpredictable regressions on out-of-distribution tasks, demonstrating that non-gradient edits lack the holistic smoothing of backpropagation.
A paper submitted to arXiv on Monday, November 9, 2026 (arXiv:2611.06120) evaluated whether interpretability vectors—such as refusal directions and truthfulness probes—can be ported between different language models using linear maps fit on unlabeled prompts. Testing across 110 model pairs spanning 1B to 72B parameters across five families, the authors demonstrated high probe recovery rates, successfully recovering 102% of refusal steering magnitude when mapped with domain-matched unlabeled text. The paper includes theoretical bounds for linear correspondence and introduces a label-free coverage metric.
Why it matters
Re-extracting probing directions and steering vectors for every newly published open-weight model version creates significant redundant labor for interpretability research. Proving that internal representation geometry can be mapped across heterogeneous models via unlabeled text allows existing probing toolkits to be instantly extended to new checkpoints. This reduces the setup overhead required for safety and capability auditing on newly released open architectures.
The paper's authors argue that shared semantic geometry across transformer architectures makes cross-model probe translation mathematically robust. Opposing analyses suggest that while linear mapping works well for global concepts like refusal or sentiment, it degrades rapidly when attempting to port fine-grained factual knowledge or complex multi-step reasoning vectors.
Researchers introduced FOSCAR on Monday, November 9, 2026, a kernel library designed to accelerate autoregressive decode attention over 2-bit and 4-bit key-value caches. Standard low-bit implementations suffer from instruction-issue stalls when applying scale and offset operations to each cache element prior to matrix multiplication. FOSCAR applies affine folding to absorb scales and offsets directly into operands and final products, reducing dequantization operations by up to two orders of magnitude. Paired with warp-specialized kernels for Hopper (H100) and Blackwell (B200) using wgmma and tcgen05 instructions, FOSCAR INT2 and INT4 kernels achieve 3.36x and 2.83x speedups over FlashInfer BF16 baselines.
Why it matters
Quantizing KV caches down to sub-3-bit formats drastically cuts memory footprint, but the dequantization math frequently saturates compute pipelines and degrades decode speeds on modern hardware. FOSCAR's algebraic affine folding removes per-element dequantization overhead, allowing Tensor Cores to operate near hardware limits. This enables high-concurrency, ultra-long-context serving without sacrificing token latency.
The authors show that folding affine parameters into matrix products resolves instruction bottlenecks in memory-bound decode passes. Systems developers note, however, that integrating custom warp-specialized kernels into general-purpose engines like SGLang requires maintaining distinct hardware execution paths for every GPU generation.
Engineers published MINE (Memory-efficient INference Engine) on Monday, November 9, 2026 (arXiv:2611.07653), a software engine using dtANS-LLM GPU entropy coding to accelerate single-stream LLM inference. MINE exploits non-uniform weight distributions remaining after low-bit quantization, auto-tuning coding parameters to compress weights down to 2.24 and 3.43 bits per weight without sacrificing accuracy. Integrated as a vLLM plugin, MINE demonstrated generation speedups of 2.52x on an RTX 4060 Ti and 1.48x on an RTX 5090 running Llama 3.1 8B Instruct over standard quantized baselines.
Why it matters
Single-stream local inference on consumer GPUs is strictly memory-bandwidth-bound, requiring every parameter to be transferred from VRAM for each generated token. By executing GPU-accelerated lossless entropy decoding on compressed weights during execution, MINE effectively increases VRAM bandwidth without requiring specialized hardware tensor layouts. This provides a direct path to higher token generation speeds on consumer GPUs.
The authors demonstrate that hardware-friendly entropy coding extracts unused bit-level redundancy from quantized weights to bypass memory bandwidth limits. Conversely, engine developers note that entropy decoding adds non-trivial compute overhead that can erode performance gains on compute-bound, high-batch server workloads.
Meituan published the full open weights for LongCat-2.5 on Hugging Face on Monday, November 9, 2026, under an unrestricted MIT license. The 1.8 TB model contains 1.6 trillion total parameters with ~48 billion active parameters per token across a mixture-of-experts architecture. Trained entirely on domestic Chinese accelerators, it incorporates native vision capabilities via multi-level Residual Vector Quantization (RVQ), scoring 88.4 on Terminal Bench v2.1 and 64.6 on DeepSWE v1.1.
Why it matters
The release provides an un-redacted 1.6T parameter MoE checkpoint under a permissive MIT license, allowing unrestricted commercial hosting and fine-tuning. The integration of native vision via RVQ eliminates separate vision encoders, offering a novel architectural reference for multimodal MoE design. However, hosting the 1.8 TB model requires multi-node cluster hardware beyond consumer reach.
Meituan highlights that LongCat-2.5 delivers top-tier terminal and SWE benchmark scores while demonstrating complete pre-training independence from Western GPU hardware. Independent deployment auditors point out that despite open licensing, self-hosting 48B active parameters requires enterprise NPU/GPU clusters, limiting local deployment to cloud-scale infrastructure.
Following last week's release of the ERNIE 5.5 Flash technical cards, Baidu has now published the raw pre-training weights to Hugging Face. As we tracked earlier, the 280-billion parameter sparse MoE activates 14 billion parameters per token and supports a 1-million-token context window. The newly available details confirm it was trained across 33.5 trillion tokens, featuring 42 MoE layers with 512 routed experts, alongside the Multi-Head Latent Attention mechanisms we previously noted.
Why it matters
While we previously covered the architecture's specifications, having the raw un-aligned base checkpoint directly available on Hugging Face provides independent researchers a massive 512-expert reference implementation for long-context sparse MoE architectures. As with the initial announcement, researchers must review Baidu's non-standard commercial usage terms prior to deployment.
Baidu emphasizes that releasing these 33.5T-token base weights enables custom domain adaptation and alignment research. However, legal analysts reiterate their warnings that the custom license includes non-standard usage restrictions—such as the revenue caps we noted previously—that require strict legal review before integration into commercial serving stacks.
Stochastic and Closed-Form Arithmetic Preserves Recurrent Memory States Rather than relying on brute-force 16-bit caching or expensive re-prefills, new studies demonstrate that low-overhead mathematical adjustments—such as stochastic rounding via integer hashes and exact linear mapping—prevent repetition loops and allow direct state transfers between heterogeneous hybrid architectures.
Scaffolding Mechanics Exert Greater Control Over Agent Scores Than Base Weights Evaluations across SWE-bench and custom agent benchmarks confirm that harness design decisions—including context indexing, tool backgrounding, and execution-grounded verification loops—account for up to seven times more variance in success rates than swapping underlying LLM backbones.
Extreme Low-Bit MoE Execution Shifts to System RAM and NVMe Tiering Maintainers of local inference runtimes are bypassing traditional GPU VRAM ceilings by pairing extreme sub-2-bit mixed quantizations with SSD streaming and host memory caching, enabling multi-hundred-billion parameter models to execute on consumer workstations.
Hardware-Fused Kernels Target Specific Dequantization Bottlenecks Engineers are moving beyond simple weight compression to address decode-step compute penalties. Techniques like affine folding and transposed softmax fusion allow Tensor Cores on modern hardware to execute 2-bit and 4-bit KV cache attention without scale-and-offset dequantization stalls.
Direct Weight Editing Challenges Gradient-Based Adaptation Interpretable parameter editing and weight-space programming are surfacing as alternatives to traditional LoRA fine-tuning. By inspecting residual stream geometries and modifying tiny fractions of layer weights, models can correct localized reasoning failures without backpropagation.
What to Expect
2026-11-29—China Ministry of Commerce (MOFCOM) public comment period closes for dual-use technology export regulations.
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